DocumentCode :
2340158
Title :
Memory BIST area estimator using Artificial Neural Networks
Author :
Lamine, Aymen ; Chouba, Nabil ; Bouzaida, Laroussi
Author_Institution :
STMicroelectronics, Ariana
fYear :
2008
fDate :
7-9 Nov. 2008
Firstpage :
1
Lastpage :
6
Abstract :
Time to market constraints pushes more and more designers to make area estimations early during the design process. Estimating the Built-In Self Test (BIST) area is only possible once the different design memories BIST are synthesized. This is time consuming and not realistic for a large circuit such as a SOC which can include hundreds of memories. In this paper we propose a push button solution for BIST area estimation called BARES based on Artificial Neuronal Networks handling. Experiments have been performed on different STMICROELECTRONICS BIST memories and results prove the efficiency of the proposed method.
Keywords :
built-in self test; integrated circuit testing; neural nets; artificial neural networks; built-in self test; memory BIST area estimator; Artificial neural networks; Automatic testing; Backpropagation algorithms; Built-in self-test; Circuit synthesis; Circuit testing; Circuits and systems; Multi-layer neural network; Neural networks; Time to market; Area estimation; Artificial Neural Network; BIST; Backpropagation algorithm; Perceptron; memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-2627-0
Electronic_ISBN :
978-1-4244-2628-7
Type :
conf
DOI :
10.1109/ICSCS.2008.4746903
Filename :
4746903
Link To Document :
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