Two Coding UARTs Low-Power Simulation Analysis Based on Gate Switching Activity Rate

Most of power consumption in CMOS chip comes from dynamic power, which is direct proportional to the parameters of gate switching activity rate (R¿) and number of gates (N). The gate switching power consumption accounts for above 80% (aiming at adder and multiplier) of total circuit\´s power consumption. By redefining this theory (R_T = count / N), and using the gate or register as analyzed "particle", we record switching numbers of all similar particles (count = R_TXN) for estimating dynamic power of circuits such as three different structural adders and two kinds of coding UART. Satisfied results show the optimization ratios of 22.5% for balance tree adder and of at least 11.1% for UART receiver in Gray coding than in Binary. Conclusions believe that understanding the probability R_T into monitoring the numbers count from amount of analyzed particles can be a simple and convenient method suited for code level dynamic power simulation.