DocumentCode
2340208
Title
VLSI hardware evaluation of the stream ciphers Salsa20 and ChaCha, and the compression function Rumba
Author
Henzen, L. ; Carbognani, F. ; Felber, N. ; Fichtner, W.
Author_Institution
Integrated Syst. Lab., ETH Zurich, Zurich
fYear
2008
fDate
7-9 Nov. 2008
Firstpage
1
Lastpage
5
Abstract
Salsa20 is a stream cipher candidate in the software-oriented profile of the eSTREAM project. ChaCha is a successor stream cipher with improved per round diffusion and, conjecturally, increased resistance to cryptanalysis. Based on the combination of four Salsa20 instances, Rumba is a compression function for hashing schemes. This paper presents the evaluation of five VLSI circuits for Salsa20. Synthesis results for a 0.18 mum CMOS technology point out that the fastest implementation achieves a throughput of 6.4Gbps, while the smallest design requires only an area of 10 k gate equivalents (GE) at 16 Mbps. This work also presents the first hardware implementations of ChaCha and Rumba. The fastest ChaCha design achieves 6.8 Gbps and the smallest design requires an area of 9.1 kGE at 16 Mbps. Furthermore, two Rumba implementations are able to achieve 17.9 Gbps or a compact area of 16.8 kGE at 12 Mbps.
Keywords
VLSI; cryptography; ChaCha; Salsa20; VLSI hardware evaluation; compression function Rumba; cryptanalysis; fastest ChaCha design; stream ciphers; CMOS technology; Circuit synthesis; Circuits and systems; Cryptography; Electronic mail; Hardware; Laboratories; Portfolios; Throughput; Very large scale integration; Stream cipher; VLSI implementation; encryption and authentication process; hash function;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on
Conference_Location
Monastir
Print_ISBN
978-1-4244-2627-0
Electronic_ISBN
978-1-4244-2628-7
Type
conf
DOI
10.1109/ICSCS.2008.4746906
Filename
4746906
Link To Document