Trimless, PVT Insensitive Voltage Reference Using Compensation of Beta and Thermal Voltage

A multiplication based CMOS process-insensitive voltage reference circuit is presented. The reference is generated by multiplying thermal voltage with forward current gain of parasitic BJT which exponentially varies with temperature. Exponential behavior of forward current gain produces inherent curvature correction. The voltage reference is designed for 152 mV. The proposed technique is analyzed theoretically and its results are compared with other methods. The circuit is designed and simulated in standard 180 nm mixed mode CMOS technology for low-cost and low-power applications. The circuit operates at minimum supply voltage of 1V with maximum drawn current of 9 μA. A temperature coefficient of 50 ppm/° C is achieved with line sensitivity of 0.11%/V. The proposed reference generator exhibits PSRR of -58.74 dB and -17.24 dB at 100 Hz and 1 MHz, respectively. The design scalability of the proposed topology is verified by reproducing almost identical performance in 90 nm mixed mode CMOS technology.