BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

The continued increase of the integration density of systems on chip (SoCs) and the number of embedded memory blocks in them, together with the continued technology scaling, increases their sensitivity to a variety of potential manufacturing (new) defects. Standard march tests are usually used to achieve a good fault/defect coverage. This paper presents an experiment in diagnosing defects in the circuitry responsible for the realization of bit, byte or group write enable in memories. First defects in such circuitry are analyzed, and fault models together with an appropriate test algorithm are presented. Subsequently, the test is added to an existing BIST engine to target the bit/byte write enable faults. The preliminary silicon results of two experiments are presented. They validate some of the targeted fault models and show the importance of considering bit/byte write enable faults for high outgoing product quality.