Layout based method to diagnose intra-gate defects in presence of multiple-fault

Diagnosis has become very important in debugging and yield improvement. Existing CAD tools are proposing solutions to locate defects at the gate level, however no one propose a method to locate defects at the transistor level. In this paper we present a new technique to diagnose intra-gate defects affecting standard cell Integrated Circuits (ICs). Our method can identify the cause of failure of different intra-gate defects such bridge, open and resistive-open defects. Our method gives accurate results since it is based on the use of physical information extracted from cellpsilas layout. Our method can also locate intra-gate defects in presence of multiple faults. Experimental results show the efficiency of our approach to isolate injected defects on industrial designs.