Extraction and simulation of potential bridging faults and open defects affecting standard cell libraries

Shorts and opens are the most common type of defects in digital integrated circuits ICs. They can affect interconnect wires connecting gates or transistors inside. Tools targeting the extraction of these potential defects focus only on the inter-gate bridging faults in order to use this information in pattern generation, and no one presents a method to extract potential intra-grate bridging fault, or open and resistive-open defects. This paper presents a new approach to automate the extraction and simulation of potential intra-gate defect in standard cell library, based on the use of verification and simulation CAD tools. Experimental results show the efficiency of our approach to identify and simulate potential intra-gate defects in 65 nm technology.