Title :
Design and implementation of 2.5 GBPS pipelined digital encoder for flash A/D Converters
Author :
Shehata, Khaled Ali ; Hussein, Hanady ; Ragai, Hani Fekri
Author_Institution :
Arab Acad. for Sci. & Technol, Cairo
Abstract :
The front-end digital encoder has become the bottleneck of the ultra-high speed flash ADCs. Pipelined digital encoder suites for 4-bit ultra high speed flash ADC is presented in this paper. It has two-stage pipelining to enhance the speed. The design is simulated and implemented using 0.18 mum UMC CMOS technology. The proposed encoder operates with 2.5 GSPS and consumes 0.8 mW. The proposed encoder effectively reduces the bubble induced error.
Keywords :
CMOS integrated circuits; analogue-digital conversion; 2.5 GBPS pipelined digital encoder; bubble induced error; flash A/D converters; front-end digital encoder; Binary codes; CMOS technology; Circuits and systems; Logic devices; Metastasis; Pipeline processing; Read only memory; Sampling methods; Signal design; Voltage; Binary code; Flash ADC; Pipelined digital encoder; thermometer code; ultra-high speed ADCs;
Conference_Titel :
Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-2627-0
Electronic_ISBN :
978-1-4244-2628-7
DOI :
10.1109/ICSCS.2008.4746926
