Effect of the integrator settling behavior on SC ΣΔ modulator characteristics: A theoretical study

The effect of the integrator settling behavior on the performances of switched-capacitor (SC) sigma-delta modulator (SigmaDeltaM) is investigated in this paper. The analysis is performed by means of behavioral simulations exploiting a new generic integrator settling model introduced to describe common high-order time responses characterizing real integrator implementations. The results of the performed investigation show that high-order poles and zeros in the integrator frequency response tend to affect even significantly the overall modulator characteristics. As a consequence when high-order integrator dynamics occur, early-design guidelines obtained from behavioral simulations based on classical first-order integrator settling descriptions can turn out to be quite rough in order to carry out a careful transistor-level modulator design. A more careful behavioral analysis based on the proposed strategy proves to be very useful to identify well-defined design specifications for the integrator in order to achieve the desired SigmaDeltaM performances avoiding costly transistor-level parameters tuning.