DocumentCode :
2341252
Title :
Fault tolerant parallel processor architecture overview
Author :
Harper, R.E. ; Lala, J.H. ; Deyst, J.J.
Author_Institution :
Charles Stark Draper Lab., Cambridge, MA, USA
fYear :
1988
fDate :
27-30 June 1988
Firstpage :
252
Lastpage :
257
Abstract :
The authors address issues central to the design and operation of a Byzantine resilient parallel computer. Interprocessor connectivity requirements are met by treating connectivity as a resource which is shared among many processing elements, allowing flexibility in their configuration and reducing complexity. Reliability analysis results are presented which demonstrate the reduced failure probability of such a system. Redundant groups are synchronized solely by message transmissions and receptions, which also provide input data consistency and output voting. Performance analysis results are presented which quantify the temporal overhead involved in executing such fault tolerance-specific operations.<>
Keywords :
computer architecture; fault tolerant computing; parallel processing; Byzantine resilient parallel computer; fault tolerant parallel processor architecture; interprocessor connectivity; output voting; reliability analysis; Application software; Circuit faults; Computer architecture; Concurrent computing; Failure analysis; Fault tolerance; Fault tolerant systems; Mission critical systems; Reliability theory; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1988. FTCS-18, Digest of Papers., Eighteenth International Symposium on
Conference_Location :
Tokyo, Japan
Print_ISBN :
0-8186-0867-6
Type :
conf
DOI :
10.1109/FTCS.1988.5328
Filename :
5328
Link To Document :
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