DocumentCode
2342283
Title
A new method to reduce power dissipation based on dynamic reconfigurable technology
Author
Wang, Yilei ; Lu, Lan ; Li, Tao
Author_Institution
Dept. of Comput. Sci. & Technol., Ludong Univ., Yantai
fYear
2009
fDate
25-27 May 2009
Firstpage
3225
Lastpage
3228
Abstract
This paper discusses the design scheme of isomerous multi-nucleus SoC2000 and CPU1 alteration of SoC2000. Double nucleus communication module design and connect style. At the last part of this paper, we put forward a new reconfigurable method - principal and subordinate CPU nucleus clock mutual closing method. This new method can not only reduce the power dissipation of SoC2000C at certain application but also can use it as single nucleus SoC to improve the product ratio.
Keywords
logic design; power aware computing; system-on-chip; CPU nucleus clock mutual closing method; double nucleus communication module design; dynamic reconfigurable technology; isomerous multinucleus SoC2000; power dissipation reduction; system on chip; Cache storage; Computer science; Decoding; Field programmable gate arrays; Frequency; HDTV; Instruction sets; Logic functions; Power dissipation; TV; Power dissipation; Reconfigureable technology; Soc2000;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4244-2799-4
Electronic_ISBN
978-1-4244-2800-7
Type
conf
DOI
10.1109/ICIEA.2009.5138797
Filename
5138797
Link To Document