Title :
Optimization of cabling in power electronics structure using inductance criterion
Author :
Piette, N. ; Clavel, E. ; Maréchal, Y.
Author_Institution :
Lab. d´´Electrotech. de Grenoble, CNRS, St. Martin d´´Heres, France
Abstract :
The power electronics applications require design of more and more structures and control of the parasitic loop inductance because of increasing current and voltage levels induced by used components (IGBT). Part of this parasitic inductance is due to imperfect connections and is directly linked to their geometrical characteristics. Therefore we present in this paper a methodology to improve the geometry of the cabling of all converters in order to limit the parasitic loop inductance, while keeping its compactness. The optimization is based on two steps: first an analysis of the structure and then the optimization of the cabling.
Keywords :
electric variables control; equivalent circuits; inductance; insulated gate bipolar transistors; optimisation; power electronics; wiring; IGBT; PEEC method; cabling optimisation; current levels; geometrical characteristics; inductance criterion; parasitic inductance; parasitic loop inductance; partial equivalent electric circuit; power electronics structure; voltage levels; Capacitors; Circuits; Geometry; Inductance; Insulated gate bipolar transistors; Optimization methods; Power electronics; Prototypes; Surges; Voltage control;
Conference_Titel :
Industry Applications Conference, 1998. Thirty-Third IAS Annual Meeting. The 1998 IEEE
Conference_Location :
St. Louis, MO, USA
Print_ISBN :
0-7803-4943-1
DOI :
10.1109/IAS.1998.730256
