Optimization of cabling in power electronics structure using inductance criterion

The power electronics applications require design of more and more structures and control of the parasitic loop inductance because of increasing current and voltage levels induced by used components (IGBT). Part of this parasitic inductance is due to imperfect connections and is directly linked to their geometrical characteristics. Therefore we present in this paper a methodology to improve the geometry of the cabling of all converters in order to limit the parasitic loop inductance, while keeping its compactness. The optimization is based on two steps: first an analysis of the structure and then the optimization of the cabling.