FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core

Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too much power as compared with other processors. The power reduction in these processors is done in the fabrication step itself. But this is a complex process. If we can implement the techniques for power reduction in front end process then we can easily design the low power processors without any complexity. In this paper we are proposing low power design in front end process. There are lot of techniques to reduce the power. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability. This RISC processor is designed using pipelined architecture; through this we can improve the speed of the operation. In this we are using 5-stage pipelining. The 5 stages are Fetch, Decode, Execute, Memory and Write Back. During the design process we are including varies low power techniques in architectural level also we are proved that our proposed methods is more efficient than back-end low power reduction techniques. Low-power embedded processors are used in a wide variety of applications including cars, phones, digital cameras, printers, and other such devices. The reason for their wide use is that they are small; therefore, they do not take up much die area and are cost effective to fabricate.