Nibble-serial: an architecture for VLSI digital signal processors

An architecture is proposed which can provide formidable processing power for the implementation of signal processing applications based on difference equations while still retaining the advantages of programmability. The architecture is based on a 4-bit-wide signal processing element (SPE), which is simple enough to be fabricated on a single VLSI circuit. The wordlength is configurable by using the requisite number of SPEs to form a processor group, and the entire chip when configured will consist of a pipeline of such processor groups. Ripple carry is used within a single SPE, with synchronous carry between the SPEs of a processor group. Performance is only slightly degraded by using longer wordlengths; however, fewer processor groups will be configurable on each chip