A study of ion implantation annealing resistance in InGaP/InGaAs/GaAs-epi structure applicable InGaAs-based HFET

A study of ion implantation annealing resistance in the InGaP/InGaAs/GaAs epi structure for HFET grown by MOCVD has been made using the Hall effect method, photoluminescence method (PL), and transmission electron microscopy observation method (TEM) comprising energy dispersive X-ray spectroscopy method (EDX). This study has revealed that resistance to annealing is minimum at the InGaAs/GaAs heterointerface where the lattice constant is greatly mismatched. The interface is considered to decay in a two-stage process. First, defects due to boundary stress are introduced in the initial phase of annealing at about 800°C. In annealing at about 850°C there is a process of recovering from these defects. It has also been revealed that this recovery process takes place at an enhanced speed according to the distribution of detects where diffusion of In from the InGaAs layer to the GaAs layer is performed. In the meantime, on the InGaP/InGaAs boundary, it has been found out that there is a process where the imperfect MOCVD epi boundary is placed in order and the boundary is clearly defined, in the initial phase of annealing. In the subsequent annealing, however, this boundary is subjected to small changes resulting from annealing, and relatively stable maintenance of the boundary structure is ensured up to 850°C.