Scavenger: An Adaptive Design Technique for Low Power ASIC/FPGA

Energy harvesting systems are becoming more attractive for remote sensing applications. In this paper, we propose a new technique that performs the voltage scaling in conjunction with frequency scaling to achieve ultra low power design in ASIC/FPGA. To detect errors and obtain the corrected data without any loss in performance, a delayed clock flip-flop is utilized to borrow timing from non-critical paths to be used in critical paths evaluation. Conservative experimental results suggest that our design technique can reduce the power consumption in FPGAs by 31%for a 100% error free operation and a 1%disagreement between the output values of the main and the delayed flip-flop. This disagreement signal,referred by the name ldquoriskrdquo in this paper, is used as a status signal to indicate drop in the available safety margins for error free operation. This approach thereby gives maximum flexibility in all three critical areas: performance, power, and robustness.