Title :
Design for hierarchical two-pattern testability of data paths
Author :
Altaf-Ul-Amin, Md ; Ohtake, Satoshi ; Fujiwara, Hideo
Author_Institution :
Nara Inst. of Sci. & Technol., Japan
Abstract :
Introduces the concept of hierarchical testability, of data paths for delay faults. A definition of a hierarchically two-pattern testable (HTPT) data path is developed. Also, a design for testability (DFT) method is presented to augment a data path to an HTPT one. The DFT method incorporates a graph-based analysis of an HTPT data path and makes use of some graph algorithms. The proposed method can provide similar advantages to the enhanced scan approach at the cost of much lower hardware overhead
Keywords :
automatic test pattern generation; delays; design for testability; fault diagnosis; graph theory; high level synthesis; logic testing; ATPG; RTL; data paths; delay defects; delay faults; design for testability; graph algorithms; graph-based analysis; hierarchical two-pattern testability; register transfer level; stuck-at faults; Algorithm design and analysis; Circuit faults; Circuit testing; Clocks; Delay; Design for testability; Hardware; Registers; Robustness; Wires;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990251
