• DocumentCode
    2342958
  • Title

    Simulation-based diagnosis for crosstalk faults in sequential circuits

  • Author

    Takahashi, Hiroshi ; Phadoongsidhi, Marong ; Higami, Yoshinobu ; Saluja, Kewal K. ; Takamatsu, Yuzo

  • Author_Institution
    Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    63
  • Lastpage
    68
  • Abstract
    Describes two methods of diagnosing crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare with observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. In these methods, if the simulated values agree with the observed responses, then the simulated fault is added to a set of suspected faults, otherwise the simulated fault is removed from the set of suspected faults. The diagnosis methods repeat the above process for each time frame to identify the suspected faults. The first method is a basic method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The second method uses state information and focuses on reducing the CPU time for diagnosing the faults. The CPU time is reduced by using stored state information to calculate the primary output values at the present time frame. Experimental results for ISCAS´89 benchmark circuits show that the number of suspected faults obtained by our methods is sufficiently small, and the second method is substantially faster than the first method
  • Keywords
    automatic testing; crosstalk; fault diagnosis; fault simulation; logic simulation; logic testing; sequential circuits; CPU time; ISCAS´89 benchmark circuits; crosstalk faults; diagnosis methods; fault simulation; observed responses; primary output values; primary outputs; pulse faults; sequential circuits; simulated values; simulation-based diagnosis; state information; suspected faults; test sequence; timeframe; Central Processing Unit; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Crosstalk; Fault diagnosis; Pulse circuits; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2001. Proceedings. 10th Asian
  • Conference_Location
    Kyoto
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-1378-6
  • Type

    conf

  • DOI
    10.1109/ATS.2001.990260
  • Filename
    990260