Title :
Test generation for double stuck-at faults
Author :
Higami, Yoshinobu ; Takahashi, Naoko ; Takamatsu, Yuzo
Author_Institution :
Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
Abstract :
In this paper, we propose a test generation method for double stuck-at faults. The proposed method consists of three main parts: (1) fault simulation with the application of test patterns generated for single stuck-at faults; (2) identification of undetectable faults; and (3) test generation using a test generator for single stuck-at faults. The effectiveness of the proposed method is shown by experimental results for ISCAS´85 benchmark circuits
Keywords :
automatic test pattern generation; combinational circuits; fault simulation; integrated circuit testing; large scale integration; logic testing; ISCAS´85 benchmark circuits; LSIs; combinational circuits; double stuck-at faults; fault simulation; logic circuits; test generation; test generator; test patterns; undetectable faults; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer science; Fault detection; Fault diagnosis; Performance evaluation; Test pattern generators;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990261
