A switching criterion for hybrid ATPG

Test pattern generation for VLSI circuits is typically performed in a hybrid environment of different automatic test pattern generation (ATPG) programs of different levels of sophistication. Here, the problem of balancing the computational load between fault simulation and conventional ATPG is addressed. A criterion for switching from fault simulation to deterministic ATPG is derived. The criterion is based on a model of monitoring the simulation process and online estimating the fault detection probabilities. Based on these probabilities a decision is made as to whether it is more advantageous to proceed with fault simulation or to switch to deterministic ATPG. For a prototype implementation of the hybrid ATPG system, significant savings in test preparation time have been measured