A three-valued fast fault simulator for scan-based VLSI-logic

Based on an effective three-valued coding, the methods of two-valued fault simulation are extended to three-valued fault simulation. Solidly and potentially detected faults are considered. Parallel processing of patterns is applied at all stages of the calculation procedure, and the expensive fault simulation is restricted to fanout stems by adopting the concept of fanout-free regions. In addition, the exploitation of the dominance relationships between signals of a combinational circuit is shown to lead not only to an acceleration of the fault-simulation process, but also to improvements in fault-detection accuracy. Experimental benchmark results substantiate the efficiency of the approach and demonstrate that three-valued fault simulation can be almost as fast as two-valued fault simulation