Title :
A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters
Author :
Wang, Chih-Wea ; Tzeng, Ruey-Shing ; Wu, Chi-Feng ; Huang, Chih-Tsun ; Wu, Cheng-Wen ; Huang, Shi-Yu ; Lin, Shyh-Horng ; Wang, Hsin-Po
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Testing and diagnosis are important issues in system-on-chip (SoC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SoC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time
Keywords :
VLSI; application specific integrated circuits; automatic test pattern generation; built-in self test; fault diagnosis; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; scheduling; ATPG; BISD compiler; BIST; SoC development; built-in self-diagnosis scheme; built-in self-test scheme; design verification; embedded SRAMs; embedded cores; heterogeneous SRAM clusters; low hardware cost; manufacturing test; memory BISD; multi-clock architectures; multiport architectures; pipelined architectures; system-onchip; test pattern generator; test scheduling methodology; yield improvement; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Fault diagnosis; Hardware; Job shop scheduling; Manufacturing; Random access memory;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990267
