Title :
IDDQ sensing technique for high speed IDDQ testing
Author :
Takeda, Teppei ; Hashizume, Masaki ; Ichimiya, Mashiro ; Yotsuyanagi, Hiroyuki ; Miura, Yukiya ; Kinoshita, Kozo
Author_Institution :
Tokushima Univ., Japan
Abstract :
In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique
Keywords :
CMOS logic circuits; automatic testing; high-speed integrated circuits; integrated circuit testing; logic gates; logic testing; CMOS logic gates; IDDQ sensing technique; circuit under test; high speed IDDQ testing; high speed tests; load capacitors; output logic level; sensor design; test input vector; CMOS logic circuits; Capacitors; Circuit faults; Circuit testing; Current measurement; Current supplies; Electrical fault detection; Fault detection; Logic gates; Logic testing;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990268
