Automatic test program generation for a block oriented VLSI chip design

Author

Hapke, Friedrich

Author_Institution

Philips RHW, Hamburg, West Germany

fYear

1989

fDate

12-14 Apr 1989

Firstpage

71

Lastpage

76

Abstract

A system for automatic test program generation is presented that is based on a block-oriented chip design. The testability is verified by a test access checker, test patterns are generated by test pattern generators, and everything is linked together by a test assembler to form a complete chip test. The testing part of the system is known as the computer-aided test (CAT) system, and consists of four programs. The function of the CAT system is to check the testability of the chip design, automatically generate test patterns for individual blocks in the chip design, and combine the test patterns for each individual block into one chip test file

Keywords

VLSI; automatic test equipment; automatic testing; electronic engineering computing; integrated circuit testing; ATE; IC testing; automatic test program generation; block oriented VLSI chip design; computer-aided test; test assembler; testability; Automatic testing; Chip scale packaging; Flip-flops; Programmable logic arrays; Read only memory; Reconfigurable logic; Sequential analysis; System testing; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1989., Proceedings of the 1st

Conference_Location

Paris

Print_ISBN

0-8186-1937-6

Type

conf

DOI

10.1109/ETC.1989.36222

Filename

36222