Sub-0.25 /spl mu/m single N/sup +/-polycide gate CMOS technology for 2.5 V applications

Sub-0.25 /spl mu/m gate length CMOS devices with N/sup +/ gate show excellent subthreshold characteristics and good suppression of short-channel effects such as punchthrough, V/sub T/ roll-off, DIBL and high-field effects. The CMOS devices are optimized by a trade-off between device driving capability and reliability. It should be pointed out that this 0.25 /spl mu/m CMOS technology using relatively thicker gate oxide (80 /spl Aring/) can be used in 3.3 V applications by further optimizing the device design and processes.