BIST and boundary-scan for board level test: test program pseudocode

A product utilizing the JTAG (Joint Test Action Group) proposed standard-scan method, architecture, and protocol (1988) is hypothesized. The product is assumed to contain a significant number of LSI and VLSI parts equipped with the proposed standard architecture and test access port (TAP). The parts equipped with boundary-scan are assumed to provide a single command activating all BIST (built-in self-test) capability which is available to the purchaser of the part in question. The pseudocode of a circuit-board test program is laid out, demonstrating the initialization of the board for testing, the necessary steps to validate the test circuitry in those ICs equipped with boundary-scan, the verification of board-level interconnect circuitry, the activation of self-test features in parts equipped with the JTAG TAP and included on the boundary-scan path, and the testing of non-boundary-scan parts on the board. The data available for diagnosis and its use in diagnosing the board are discussed briefly