Guardband determination for the detection of off-state and junction leakages in DRAM testing

The chips with defects, which escape the test, will cause quality problems, damage the goodwill and decline the revenue. It is important to look for a set of effective and efficient tests in the production line. In this paper, a case study of SDRAM (Synchronous DRAM)/SGRAM (Synchronous Graphics RAM) is used to demonstrate the guardband determination of testing the off-state and junction leakages in the silicon debug stage for production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low-test cost. The electrical modeling of DRAM cell, test selection and guardband determination are introduced. It is shown that the newly created tests can distinguish the normal and abnormal cell current leakages. Promising wafer test results are obtained that the wafer test yield is improved over 8% by laser repairing the weak (defective) cells with the spares and it achieves a reasonable final test quality