Title :
Simulation and development of short transparent tests for RAM
Author :
Demidenko, S. ; Van De Goor, A. ; Henderson, S. ; Knoppers, P.
Author_Institution :
Inst. of Inf. Sci. & Technol., Massey Univ., Palmerston North, New Zealand
Abstract :
Short transparent memory test algorithms for semiconductor memories are presented along with an evaluation of the space on silicon required for their built-in self-test implementation. A modified version of the memory test simulation package MAP+ has been developed and employed for test algorithms generation and simulation
Keywords :
VLSI; automatic test pattern generation; built-in self test; circuit simulation; fault diagnosis; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; ATPG; BIST implementation; MAP+ package; March tests; built-in selftest implementation; embedded RAM; fault models; memory test algorithms; memory test simulation package; random access memories; semiconductor memories; short transparent tests; test algorithms generation; test algorithms simulation; Automatic testing; Circuit simulation; Circuit testing; Electronic equipment testing; Logic testing; Packaging; Random access memory; Read-write memory; Resource description framework; Space technology;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990276
