Title :
A GALS Network-on-Chip based on rationally-related frequencies
Author :
Chabloz, Jean-Michel ; Hemani, Ahmed
Author_Institution :
Dept. of Electron. Syst., KTH - R. Inst. of Technol., Stockholm, Sweden
Abstract :
GALS Networks-on-Chip (NoCs) in which the frequency of every switch can be set independently would enable per-node DVFS without requiring asynchronous switch design. However, traditional GALS interfaces introduce high latency penalties and are therefore ill-suited for inter-switch links in a NoC. In this paper we introduce and study a GALS Network-on-Chip based on the Globally-Ratiochronous, Locally-Synchronous (GRLS) paradigm. GRLS constrains all switch frequencies to be rationally-related but enables the use of efficient interfaces which reduce the latency of the network 60% compared to GALS solutions and obtains better throughput-per-power ratios compared to synchronous and mesochronous solutions.
Keywords :
circuit switching; network-on-chip; power aware computing; GALS network-on-chip; NoC; globally-ratiochronous locally-synchronous paradigm; high latency penalties; inter-switch links; per-node DVFS; rationally-related frequencies; throughput-per-power ratios; Clocks; Frequency conversion; Radiation detectors; Receivers; Switches; Synchronization; Transmitters;
Conference_Titel :
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location :
Amherst, MA
Print_ISBN :
978-1-4577-1953-0
DOI :
10.1109/ICCD.2011.6081369