DocumentCode
2343384
Title
An approach to RTL fault extraction and test generation
Author
Yin, Zhigang ; Min, Yinghua ; Li, Xiaowei
Author_Institution
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
fYear
2001
fDate
2001
Firstpage
219
Lastpage
224
Abstract
The paper presents an approach to fault extraction and test generation at RTL (register transfer level). The proposed ATPG (automatic test pattern generation) is targeting to cover all the extracted faults rather than a specific fault, and based on simulation with unspecified inputs. It uses a request-echo strategy called X-Pulling to greatly reduce the unnecessary backtrack and implication, which makes the algorithm very efficient. Experimental results demonstrate that our approach is better than ARTIST in three aspects: on average, the CPU time is shorter by three orders of magnitude, the test length is shorter by 52% and the fault coverage is higher by 0.89%
Keywords
automatic test pattern generation; fault diagnosis; high level synthesis; logic testing; ATPG; CPU time; RTL fault extraction; RTL test generation; X-Pulling; automatic test pattern generation; fault coverage; request-echo strategy; test length; unspecified inputs; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Computers; Genetic algorithms; Observability; Registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location
Kyoto
ISSN
1081-7735
Print_ISBN
0-7695-1378-6
Type
conf
DOI
10.1109/ATS.2001.990285
Filename
990285
Link To Document