• DocumentCode
    2343406
  • Title

    A tool set for the design of asynchronous circuits with bundled-data implementation

  • Author

    Iizuka, Minoru ; Hamada, Naohiro ; Saito, Hiroshi ; Yamaguchi, Ryoichi ; Yoshinaga, Minoru

  • Author_Institution
    Univ. of Aizu, Fukushima, Japan
  • fYear
    2011
  • fDate
    9-12 Oct. 2011
  • Firstpage
    78
  • Lastpage
    83
  • Abstract
    This paper proposes a tool set for the design of asynchronous circuits with bundled-data implementation. Using the proposed tool set with commercial CAD tools, asynchronous circuits with bundled-data implementation can be designed easily. Through the experiments, this paper evaluates synthesized circuits using the proposed tool set in terms of area, performance, power consumption, and energy consumption comparing with synchronous counterparts.
  • Keywords
    asynchronous circuits; network synthesis; asynchronous circuit design; bundled-data implementation; commercial CAD tool; energy consumption; power consumption; synthesized circuit; tool set; Asynchronous circuits; Delay; Integrated circuit modeling; Registers; Solid modeling; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2011 IEEE 29th International Conference on
  • Conference_Location
    Amherst, MA
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4577-1953-0
  • Type

    conf

  • DOI
    10.1109/ICCD.2011.6081379
  • Filename
    6081379
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2343406