Title :
Hazards effect on stuck-open fault testability
Author :
Landrault, C. ; Pravossoudovitch, S.
Author_Institution :
Lab. d´´Autom. et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
Testing of stuck-open faults requires sequences of input vectors. The authors discuss test invalidation problems produced by hazard switching due to internal delays or timing skews in input changes. To avoid invalidation possibilities in stuck-open fault-test sequences, the proposed solutions lead to structural modifications of the circuit or robust test sequences composed of more than two vectors
Keywords :
CMOS integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS; IC testing; MOS IC; VLSI; hazard switching; internal delays; robust test sequences; structural modifications; stuck-open fault testability; CMOS technology; Circuit faults; Circuit testing; Delay; Hazards; Logic testing; Robustness; Semiconductor device modeling; Test pattern generators; Timing;
Conference_Titel :
European Test Conference, 1989., Proceedings of the 1st
Conference_Location :
Paris
Print_ISBN :
0-8186-1937-6
DOI :
10.1109/ETC.1989.36244
