DocumentCode :
2343439
Title :
Applying verification intention for design customization via property mining under constrained testbenches
Author :
Chung, Chih-Neng ; Chang, Chia-Wei ; Chang, Kai-Hui ; Kuo, Sy-Yen
Author_Institution :
GIEE, Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2011
fDate :
9-12 Oct. 2011
Firstpage :
84
Lastpage :
89
Abstract :
Most synthesis tools perform optimizations based on the design itself and do not utilize the information present in the verification environment. Not using such information greatly limits the optimization capabilities of synthesis tools, which is especially serious for circuit customization because most environment constraints are encoded in the testbench. To exploit verification intention, we propose a methodology that utilizes functional assertions for design optimization. To support circuit customization, we also propose a property mining technique that can extract properties from the design under the constraints in the testbench. Our experimental results show that these methods can reduce design size after synthesis, and the optimization is orthogonal to other existing circuit customization methods.
Keywords :
circuit optimisation; formal verification; logic design; logic simulation; circuit customization; constrained testbenches; design customization; design optimization; design size; environment constraints; functional assertions; optimization capability; property mining technique; synthesis tools; verification environment; verification intention; Algorithm design and analysis; Design optimization; Integrated circuit modeling; Pattern matching; Reactive power; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location :
Amherst, MA
ISSN :
1063-6404
Print_ISBN :
978-1-4577-1953-0
Type :
conf
DOI :
10.1109/ICCD.2011.6081380
Filename :
6081380
Link To Document :
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