Title :
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Author :
Bonhomme, Y. ; Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S.
Author_Institution :
Lab. d´´Informatique de Robotique et de Microelectronique de Montpellier, Univ. Montpellier II/CNRS, France
Abstract :
Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique
Keywords :
application specific integrated circuits; automatic testing; boundary scan testing; clocks; design for testability; integrated circuit testing; logic testing; low-power electronics; clock rate; clock tree; design-for-testability; embedded cores; gated clock scheme; logic ICs; low power scan testing; power consumption; scan path; shift operations; test power; test time; Circuit testing; Clocks; Costs; Logic design; Logic testing; Power dissipation; Robots; Switches; System testing; Uniform resource locators;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990291
