Title :
Test scheduling and scan-chain division under power constraint
Author :
Larsson, Erik ; Peng, Zebo
Author_Institution :
Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
Abstract :
An integrated technique for test scheduling and scan-chain division under power constraints is proposed in this paper. We demonstrate that optimal test time can be achieved for systems tested by an arbitrary number of tests per core using scan-chain division and we define an algorithm for it. The design of wrappers to allow different lengths of scan-chains per core is also outlined. We investigate the practical limitations of such wrapper design and make a worst case analysis that motivates our integrated test scheduling and scan-chain division algorithm. The efficiency and usefulness of our approach have been demonstrated with an industrial design
Keywords :
VLSI; application specific integrated circuits; automatic testing; integrated circuit testing; scheduling; SoC testing; integrated technique; optimal test time; power constraints; scan-chain division; system-on-chip; test scheduling; wrapper design; Algorithm design and analysis; Automatic testing; Built-in self-test; Information science; Job shop scheduling; Performance evaluation; Processor scheduling; Scheduling algorithm; System testing; System-on-a-chip;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990292
