• DocumentCode
    2343507
  • Title

    Resource allocation and test scheduling for concurrent test of core-based SOC design

  • Author

    Huang, Yu ; Cheng, Wu-Tung ; Tsai, Chien-Chung ; Mukherjee, Nilanjan ; Samman, Omer ; Zaidan, Yahya ; Reddy, Sudhakar M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    265
  • Lastpage
    270
  • Abstract
    A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results
  • Keywords
    application specific integrated circuits; bin packing; concurrent engineering; design for testability; integrated circuit testing; scheduling; 2-dimensional bin-packing problem; TAM; best-fit heuristic algorithm; concurrent test; core-based SOC design; design phase; resource allocation; test access mechanism; test application time; test budgeting; test scheduling; Cities and towns; Computer graphics; Job shop scheduling; Pins; Processor scheduling; Rails; Resource management; Scheduling algorithm; System testing; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2001. Proceedings. 10th Asian
  • Conference_Location
    Kyoto
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-1378-6
  • Type

    conf

  • DOI
    10.1109/ATS.2001.990293
  • Filename
    990293