A unified scheme for designing testable state machines

Author

Lala, P.K. ; Walker, A.

Author_Institution

Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA

fYear

2001

fDate

2001

Firstpage

273

Lastpage

278

Abstract

An approach for designing state machines that have built-in on-line and off-line testability is proposed. The next state logic is designed using transmission gates and tri-state buffers only. The resulting machines have scan-in/scan-out capability that allows off-line testing of the next state logic. The on-line testing capability for erroneous state transitions is achieved by EX-ORing the outputs of two registers that store the current and the next state of a machine, and checking for even parity at the outputs of the EX-OR gates

Keywords

boundary scan testing; buffer circuits; fault diagnosis; finite state machines; logic gates; logic testing; state assignment; EX-OR gates; benchmarks; erroneous state transitions; even parity; next state logic; off-line testability; on-line testability; scan-in/scan-out capability; state assignment; testable state machines; transmission gates; tri-state buffers; unified scheme; Circuit faults; Circuit synthesis; Circuit testing; Clocks; Combinational circuits; Computer science; Design engineering; Electrical fault detection; Logic design; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2001. Proceedings. 10th Asian

Conference_Location

Kyoto

ISSN

1081-7735

Print_ISBN

0-7695-1378-6

Type

conf

DOI

10.1109/ATS.2001.990295

Filename

990295