DocumentCode :
2343519
Title :
An optimized scaled neural branch predictor
Author :
Jiménez, Daniel A.
Author_Institution :
Dept. of Comput. Sci., Univ. of Texas at San Antonio, San Antonio, TX, USA
fYear :
2011
fDate :
9-12 Oct. 2011
Firstpage :
113
Lastpage :
118
Abstract :
Conditional branch prediction remains one of the most important enabling technologies for high-performance microprocessors. A small improvement in accuracy can result in a large improvement in performance as well as a significant reduction in energy wasted on wrong-path instructions. Neural-based branch predictors have been among the most accurate in the literature. The recently proposed scaled neural analog predictor, or SNAP, builds on piecewise-linear branch prediction and relies on a mixed analog/digital implementation to mitigate latency as well as power requirements over previous neural predictors. We present an optimized version of the SNAP predictor, hybridized with two simple two-level adaptive predictors. The resulting optimized predictor, OH-SNAP, delivers very high accuracy compared with other state-of-the-art predictors.
Keywords :
microprocessor chips; OH-SNAP; SNAP predictor; adaptive predictor; conditional branch prediction; high-performance microprocessor; mixed analog-digital implementation; optimized scaled neural branch predictor; piecewise-linear branch prediction; Accuracy; Arrays; History; Optimization; Prediction algorithms; Training; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location :
Amherst, MA
ISSN :
1063-6404
Print_ISBN :
978-1-4577-1953-0
Type :
conf
DOI :
10.1109/ICCD.2011.6081385
Filename :
6081385
Link To Document :
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