Enhancing BIST quality of sequential machines through degree-of-freedom analysis

Author

Sikdar, Biplab K. ; Roy, Samir ; Das, Debesh K.

Author_Institution

Dept. of Comput. Sci. & Technol., Bengal Eng. Coll., Howrah, India

fYear

2001

fDate

2001

Firstpage

285

Lastpage

290

Abstract

Designing a BIST structure for sequential circuits is rather a complex problem as some states remain unreachable and some act as the sink under any input sequence. This paper reports an efficient scheme to provide uniform mobility, referred to as degree of freedom, in a sequential machine by enhancing the reachability as well as the emittability of the states. The uniform mobility of states ensures higher fault efficiency in a BIST structure of the circuit. Moreover, as a non-scan scheme, the technique provides lower test application time and at-speed testing

Keywords

VLSI; automatic testing; built-in self test; fault diagnosis; integrated circuit testing; sequential circuits; sequential machines; BIST quality; VLSI; at-speed testing; degree of freedom; degree-of-freedom analysis; emittability; fault efficiencies; fault efficiency; input sequence; nonscan scheme; reachability; sequential circuits; sequential machines; test application time; uniform mobility; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Flip-flops; Sequential analysis; Sequential circuits; Strontium; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2001. Proceedings. 10th Asian

Conference_Location

Kyoto

ISSN

1081-7735

Print_ISBN

0-7695-1378-6

Type

conf

DOI

10.1109/ATS.2001.990297

Filename

990297