DocumentCode
2343589
Title
Test and screening strategies for large memories
Author
Birolini, A. ; Büchel, W. ; Heavner, D.
Author_Institution
Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Zurich, Switzerland
fYear
1989
fDate
12-14 Apr 1989
Firstpage
276
Lastpage
283
Abstract
The possibilities and limits of testing and screening large memories are reviewed. Practical results are given. The procedures for the qualification test of different types of memories are discussed. The concept of test strategy is introduced. Future trends in testing large memories are presented. It is shown that AC, functional, and DC test should be performed under several different conditions to help determine the correct testing strategy
Keywords
VLSI; computer equipment testing; integrated circuit testing; integrated memory circuits; logic testing; reliability; AC test; DC test; IC testing; VLSI; functional test; large memories; logic testing; qualification test; reliability; screening strategies; test strategy; Costs; Inspection; Logic testing; Performance evaluation; Protection; Qualifications; Redundancy; Safety devices; Sampling methods; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
European Test Conference, 1989., Proceedings of the 1st
Conference_Location
Paris
Print_ISBN
0-8186-1937-6
Type
conf
DOI
10.1109/ETC.1989.36254
Filename
36254
Link To Document