DocumentCode :
2343609
Title :
Testability strategy for registers and memories in a multi-processor architecture
Author :
Van Sas, Jos ; Catthoor, Francky ; Inzé, Luc ; De Man, Hugo
Author_Institution :
IMEC Lab., Leuven, Belgium
fYear :
1989
fDate :
12-14 Apr 1989
Firstpage :
294
Lastpage :
303
Abstract :
A testability strategy is presented for registers and memories embedded in multiprocessor chips designed with the Cathedral-II silicon compilation environment. The implementation requires the design of a scan register that is able to maintain a value at its output while scanning a vector into the scan chain. A test algorithm for the register file, based on the concept of C-testability, is derived. The fault model covers both stuck-at and most of the transistor stuck-open and stuck-close cases. In addition, large embedded memories are important in processor systems. A test strategy with very high fault coverage is implemented with a self-test approach
Keywords :
circuit CAD; computer architecture; computer equipment testing; fault location; integrated memory circuits; logic testing; multiprocessing systems; shift registers; C-testability; Cathedral-II silicon compilation environment; computer equipment testing; embedded memories; fault model; multi-processor architecture; multiprocessor chips; register file; scan chain; scan register; self-test; stuck-at; stuck-close; stuck-open; test algorithm; testability strategy; Built-in self-test; Digital signal processing; Laboratories; Master-slave; Read-write memory; Registers; Routing; Signal processing algorithms; Silicon; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Test Conference, 1989., Proceedings of the 1st
Conference_Location :
Paris
Print_ISBN :
0-8186-1937-6
Type :
conf
DOI :
10.1109/ETC.1989.36256
Filename :
36256
Link To Document :
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