Title :
Testing regular arrays: the boundary problem
Author :
Marnane, W.P. ; Moore, W.R.
Author_Institution :
Dept. of Eng. Sci., Oxford Univ., UK
Abstract :
The authors present a unifying approach to the testing of fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. It includes the often overlooked but nontrivial problem of observing the fault effects, especially at the edges of the arrays. The problems and possible solutions are illustrated using the example of a systolic correlator
Keywords :
VLSI; cellular arrays; fault location; integrated circuit testing; logic arrays; logic testing; IC testing; boundary; edges; fault effects; fine-grained VLSI arrays; regular arrays; systolic correlator; test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Correlators; Fault detection; Integrated circuit interconnections; Logic testing; Semiconductor device modeling; Test pattern generators; Very large scale integration;
Conference_Titel :
European Test Conference, 1989., Proceedings of the 1st
Conference_Location :
Paris
Print_ISBN :
0-8186-1937-6
DOI :
10.1109/ETC.1989.36257
