Title :
Fault simulation for delay faults
Author :
Oomman, Bejoy G. ; Akers, Sheldon B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Methods to quantify the effectiveness of a delay test are presented. The notion of hazard insensitivity, which generalizes the notion of a robust delay test, is used to identify instances of test invalidation due too glitches. The delay fault-simulator is used to evaluate some built-in-self-test (BIST) schemes. The delay-fault simulator is built around a stuck-at fault simulator. This makes the overall fault-simulation process very efficient. Based on this, three measures of delay-fault coverage are defined. A BIST scheme for level-sensitive-scan design environment with improved delay-fault detection capabilities is proposed
Keywords :
delays; digital simulation; fault location; logic testing; BIST; built-in-self-test; delay faults; glitches; level-sensitive-scan design; logic testing; robust delay test; stuck-at fault simulator; test invalidation; Circuit faults; Circuit testing; Clocks; Delay effects; Hazards; Latches; Logic circuits; Logic testing; Propagation delay; Robustness;
Conference_Titel :
European Test Conference, 1989., Proceedings of the 1st
Conference_Location :
Paris
Print_ISBN :
0-8186-1937-6
DOI :
10.1109/ETC.1989.36260
