Title :
UTILE system: a unified environment from simulation to test
Author :
Becu, Jean-Luc ; Bouzaida, L.
Author_Institution :
SGS-Thomson Microelectron., Grenoble, France
Abstract :
The UTILE (unified test integrated language and environment) system, a unified environment from simulation to test for logic circuits, is described. The system is built around a high-level algorithmic language to describe simulation sequences in terms of functional cycles. The environment provided is independent of the simulator used and the test system, and makes it possible to perform simulation and test-related tasks, from circuit validation to test program generation
Keywords :
digital simulation; high level languages; logic CAD; logic testing; circuit validation; functional cycles; high-level algorithmic language; logic CAD; logic circuits; simulation; test program generation; unified environment; unified test integrated language and environment; Application specific integrated circuits; Circuit simulation; Circuit testing; Logic circuits; Logic testing; Performance evaluation; Production; Research and development; System testing; Test equipment;
Conference_Titel :
European Test Conference, 1989., Proceedings of the 1st
Conference_Location :
Paris
Print_ISBN :
0-8186-1937-6
DOI :
10.1109/ETC.1989.36265
