DocumentCode :
2343950
Title :
Short circuit faults in state-of-the-art ADCs - are they hard or soft?
Author :
Lechner, A. ; Richardson, A. ; Hermes, B.
Author_Institution :
Fac. of Appl. Sci., Lancaster Univ., UK
fYear :
2001
fDate :
2001
Firstpage :
417
Lastpage :
422
Abstract :
For next generation deep sub-micron (DSM) analogue and mixed signal ICs, the integration of Design-for-Test (DfT), Design for-Manufacturability (DfM), Defect-Oriented Test (DOT) approaches, and Built-In Self-Test (BIST) techniques into the design and manufacturing cycle will gain increasing importance to the context of implementing a structural IC test methodology (1). This paper discusses the relevance of fault simulation techniques to investigate realistic circuit failure modes and test requirements. It is shown for an ADC target design that hard faults frequently cause marginal rather than catastrophic failure, hence have to be subject to test
Keywords :
analogue-digital conversion; automatic testing; built-in self test; circuit CAD; design for manufacture; design for testability; failure analysis; fault simulation; logic design; mixed analogue-digital integrated circuits; probability; short-circuit currents; BIST; Built-In Self-Test; Design-for-Manufacturability; Design-for-Test; deep sub-micron analogue signal ICs; defect oriented test; mixed signal ICs; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for manufacture; Design for testability; Integrated circuit testing; Manufacturing; Signal design; US Department of Transportation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
ISSN :
1081-7735
Print_ISBN :
0-7695-1378-6
Type :
conf
DOI :
10.1109/ATS.2001.990319
Filename :
990319
Link To Document :
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