An embedded built-in-self-test approach for digital-to-analog converters

Author

Jeng-Horng, T. ; Hsiao, Ming-Jun ; Chang, Tsin-Yuan

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2001

fDate

2001

Firstpage

423

Lastpage

428

Abstract

Without a large number of precision reference voltages and with the consideration of matching problems, a builtin-self-test approach is proposed to test the parameters of digital-to-analog converter (DAC), which includes offset error (VOSE); gain error (GFSE), differential nonlinearity (DNL) error, and integral nonlinearity (INL) error. The proposed structure is designed and simulated in an 8-bit DAC by using TSMC 0.35 μm 2P4M process. The accuracy of offset error test, gain error test, and DNL test are all beneath 1/11 LSB for 8-bit DAC at 5V supply voltage, and the accuracy of INL test depends on the testing time. The longer testing time, the more accurate is

Keywords

built-in self test; design for testability; digital-analogue conversion; integrated circuit testing; 0.35 μm 2P4M process; 0.35 micron; 5 V; 5V supply voltage; 8-bit DAC; BIST; CMOS comparator; auto-zero circuit; builtin-self-test; differential nonlinearity error; digital-to-analog converter; gain error; integral nonlinearity error; negative ramp generator; precision reference voltages; Built-in self-test; Circuit testing; Controllability; Costs; Digital-analog conversion; Integrated circuit testing; Observability; Signal processing; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2001. Proceedings. 10th Asian

Conference_Location

Kyoto

ISSN

1081-7735

Print_ISBN

0-7695-1378-6

Type

conf

DOI

10.1109/ATS.2001.990320

Filename

990320