An application of partial scan techniques to a high-end system LSI design

In large and high-speed LSI designs, the area and delay overhead of the design-for-test (DFT) circuit must be minimized while keeping sufficient testability. Partial scan is one of the techniques that can reduce the overhead of full scan. However, it is not simple to apply the partial scan method to large designs because of its long design turn-around-time (TAT) and pattern length. This paper presents an application of the partial scan method to a real LSI design. Several techniques have been introduced in order to effectively apply the method to the large high-end system LSI