Title :
A low-power LFSR architecture
Author :
Huang, Tsung-Chu ; Lee, Kuen-Jong
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes. The clock and data input capacitances of a latch are assumed the same as that of a regular gate. A double-latch FF thus consumes 5 transitions including the interconnection between latches when the data changes
Keywords :
built-in self test; clocks; demultiplexing equipment; flip-flops; low-power electronics; pulse generators; sequential circuits; shift registers; BIST; data input capacitances; double-latch FF; interconnection; internal gates; low-power LFSR architecture; multiphase clock generator; static demultiplexers; weighted transition count; Built-in self-test; Circuit testing; Circuits and systems; Clocks; Counting circuits; Latches; Logic; Power dissipation; Power generation; Strontium;
Conference_Titel :
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location :
Kyoto
Print_ISBN :
0-7695-1378-6
DOI :
10.1109/ATS.2001.990337
