DocumentCode :
2344636
Title :
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling
Author :
Jafari, Fahimeh ; Jantsch, Axel ; Lu, Zhonghai
Author_Institution :
R. Inst. of Technol. (KTH), Stockholm, Sweden
fYear :
2011
fDate :
9-12 Oct. 2011
Firstpage :
445
Lastpage :
446
Abstract :
In NoCs often several flows are merged into one aggregate flow due to heavy resource sharing. For strengthening formal performance analysis, we propose an improved model for an output flow of a FIFO multiplexer under aggregate scheduling. The model of the aggregate flow is formally proven and can serve as the basis for a stringent worst case delay and buffer analysis.
Keywords :
network-on-chip; performance evaluation; scheduling; FIFO multiplexer; NoC; aggregate flow model; aggregate scheduling; buffer analysis; first-in first-out; formal performance analysis; network-of-chips; on-chip network; stringent worst case delay analysis; variable bit-rate flow; Aggregates; Analytical models; Calculus; Delay; Multiplexing; Real time systems; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location :
Amherst, MA
ISSN :
1063-6404
Print_ISBN :
978-1-4577-1953-0
Type :
conf
DOI :
10.1109/ICCD.2011.6081442
Filename :
6081442
Link To Document :
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