Title :
The iFlow design factory infrastructure for a 17M-gate, 0.13μm, 333MHz design [SoC design]
Author :
Descamps, Gilles-Eric ; Bagalkotkar, Satish
Author_Institution :
Silicon Access Networks, San Jose, CA, USA
Abstract :
To be able to meet the aggressive time-to-market requirements, and solve the challenges inherent to the multi-site design of large system-on-a-chips (SoCs), Silicon Access Networks had to evolve its art of chip design into an industrial process. This contribution describes a unique infrastructure which is quality-driven rather than time-committed. The chip design process is streamlined, visible, and measured, achieving predictability. By managing resources, Silicon Access Networks realized significant savings in time and maximized its return on investment (ROI). Bring-up and pre-production showed that first silicon met all its targets: power, speed, yield and complete functionality with no mask change. Four chips were designed using state-of-the-art 0.13 μm technology and collectively represent 730-million transistors, implementing a variety of analog, digital, high-speed memory, and functional blocks.
Keywords :
circuit CAD; integrated circuit design; integrated memory circuits; system-on-chip; 0.13 micron; 333 MHz; SoC design; analog blocks; design factory infrastructure; digital blocks; functional blocks; high-speed memory blocks; multi-site design; quality-driven infrastructure; system-on-a-chip; Art; Chip scale packaging; Investments; Power system management; Production facilities; Resource management; Semiconductor device measurement; Silicon; System-on-a-chip; Time to market;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249353
